1. Field of the Invention
The present invention relates to a nonvolatile ferroelectric memory device, and more specifically, to a nonvolatile ferroelectric memory device having a test circuit which can selectively test more than 2 cell array blocks at the same time without modifying an internal circuit.
2. Description of the Prior Art
Generally, a ferroelectric random access memory (FeRAM) has the data processing speed as fast as a Dynamic Random Access Memory (DRAM), and also retains data even in a power-off state. For this reason, the nonvolatile ferroelectric memory has attracted considerable attention as a next generation memory device.
The FeRAM has a structure similar to DRAM, and employs ferroelectric material for a capacitor to use a high residual polarization characteristic of the FeRAM. The residual polarization characteristic protects data from erasing even when electric field is removed.
FIG. 1 illustrates a unit memory cell of a conventional nonvolatile memory device.
The unit memory cell of the conventional FRAM is provided with a bitline BL arranged in one direction, a wordline WL arranged perpendicular to the bitline and a plateline PL arranged in parallel to the wordline and spaced at a predetermined interval. The unit memory cell is also provided with a transistor T1 having a gate connected to an adjacent wordline WL and a source connected to an adjacent bitline BL, and a ferroelectric capacitor FC having two electrodes respectively connected to an electrode of the NMOS transistor T1 and the plateline PL.
FIG. 2 is a block diagram illustrating the configuration of cell array of a nonvolatile ferroelectric memory.
Cell array blocks BLK0˜BLKn are symmetrically located above and below common data buses BUS(0)˜BUS(n), and each main bitline MBL of the cell array blocks BLK0˜BLKn is selectively connected with the data buses BUS(0)˜BUS(n) by a column selecting unit CS. The cell array blocks BLK0˜BLKn have a multi-bitline structure, each main bitline comprising a plurality of sub bitlines (not shown). The sensing voltage of the sub bitlines is converted to the electric current to induce the sensing voltage of the main bitline MBL. The induced sensing voltage of the main bitline MBL is transmitted to a corresponding sense amplifier of a sense amplifier array 10 through the data buses BUS(0)˜BUS(n) and then sensed. Each of the common data buses BUS(0)˜BUS(n) is connected with one main bitline MBL of each cell array block BLK(0)˜BLK(n).
FIG. 3 is a circuit diagram illustrating the configuration of the cell array block BLK0 having a multi-bitline structure and the column selecting unit CS of FIG. 2.
The sub bitlines SBL are connected to a plurality of memory cells having a 1T1C (1 Transistor 1 Capacitor) structure connected between wordlines WL(0)˜WL(m-1) and platelines PL(0)˜PL(m-1). The sub bitlines SBL transmit data loaded on itself to a main bitline MBL by activating a sub bitline selecting signal SBSW1 and then turning on a NMOS transistor T3. Accordingly, a main bitline MBL is connected to one sub bitline at a time. Also, a sub bitline SBL is controlled to become a ground voltage level when a sub bitline pull-down signal SBPD is activated to turn on a NMOS transistor T4.
A sub bitline pull-up signal SBPU is a control signal for controlling a power supply supplied to a sub bitline SBL, and a sub bitline selecting signal SBSW2 controls the flow of signals between the sub bitline pull-up signal SBPU and a sub bitline SBL.
The main bitline MBL is selectively connected to a common data bus BUS(0) by the column selecting unit CS which is turned on/off depending on a column selecting signal CS0.
FIG. 4 is a timing diagram explaining the operation of FIG. 3.
When a wordline WL(0) and a plate line PL(0) is activated to a high level, the voltage levels of sub bitline SBL and main bitline MBL are determined according to the data value of the relevant memory cell. For examples, when cell data is “HIGH”, the voltage level of sub bitline BL goes up much, and thereby the amount of current flowing through a NMOS transistor T6 is increased much so that the voltage level of main bitline falls much. On the contrary, when cell data is “LOW”, the voltage level of sub bitline SBL goes up a little, and thereby the amount of current flowing through the NMOS transistor T6 is reduced so that the voltage level of main bitline MBL falls a little. That is to say, the difference of voltage level in a main bitline MBL is due to cell data.
As shown above, as a result of testing a standard cell having a 1T1C structure, when fail is occurred in some cell array blocks, they are repaired to be used. Particularly, when fail is occurred per a cell array block, failed cell array blocks and normal cell array blocks are combined to be used as 2T2C, 4T4C or 8T8C structure. For examples, when a cell array block BLK0 is failed, it is combined with a normal cell array block BLK1 symmetrically located around the central common data buses BUS(0)˜BUS(n) to be used as 4T4C structure, or it is combined with normal cell array blocks BLK1-BLK7 to be repaired as 8T8C structure.
However, as shown above, an additional process for modifying an internal circuit is required to test the operation of repaired memory device after repairing it as 2T2C, 4T4C or 8T8C structure. Accordingly, additional costs and time are required for performing this process.